It is known in data processing apparatuses to arrange the storage of data in memory in a page mapped manner, wherein page tables stored in external memory provide a translation between virtual addresses used by a program running in the data processing apparatus and physical addresses of data in external memory. A memory management unit (MMU) is typically provided to administer these translations. Using page mapped memory for a master device in a system through a MMU has the advantage of allowing its operation to be integrated with the memory management of the operating system and enables memory protection shielding from one application to another.
The MMU is normally arranged to have an internal storage unit in which a cached subset of all possible translations between virtual and physical addresses is stored. A typical example of such an internal storage unit is a translation lookaside buffer (TLB). When the MMU receives a memory access request from a master device in the data processing apparatus, it references its TLB to establish if an entry corresponding to that virtual address is currently stored therein. If it is, then the MMU translates the virtual address into the corresponding physical address using the information in the TLB entry and the memory access request is carried out using that physical address. If however an entry corresponding to the requested virtual address is not stored in the TLB, then the MMU initiates a “page walk” process in which a page table stored in external memory is referenced to find the virtual address. A replacement entry for that entry of the TLB is retrieved from the page table (consisting of an indication of the virtual address to physical address translation and, typically, some other permission information). The physical address in memory is then accessed.
It is further known for a data processing apparatus to comprise multiple master devices which can issue memory access requests including virtual addresses that require translation into corresponding physical addresses. Such a multi-master device may only provide a single MMU (comprising a single TLB). Such a shared MMU/TLB has the advantage of occupying a limited area on a system-on-chip (SoC) device. However, such an arrangement also has the drawback that the activities of one master device may adversely affect the performance of another master device, for example where a TLB entry commonly used by one master is the same as a commonly used TLB entry for another master. The thrashing that then results due to each master repeatedly replacing that TLB entry can be a serious performance limitation.
One known mechanism for identifying TLB entries in a system having multiple masters is the addition of an extra bit in each TLB entry indicating the master to which that TLB entry belongs. Whilst such an arrangement can enable the MMU to keep track of which TLB entries are associated with which master devices, the above described problem of thrashing between different masters using the same TLB entry can still occur. Furthermore this approach necessarily increases the size of each TLB entry.
It would be desirable to provide an improved technique for the configuration of a memory management unit servicing a number of master devices.